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System-on-Chip Design (09_O-CSP) ​

  • Coefficient : 6
  • Hourly Volume: 150h (including 72h supervised)
    CTD : 24h supervised
    Labo : 48h supervised (and 12h unsupervised)
    Out-of-schedule personal work : 66h
  • Including project : 27h supervised and 27h unsupervised project

AATs Lists

Description ​

The structuring of the design, the evaluation of its performances and its modeling in HDL (Hardware Description Language) are studied. The tools and methods of integration into a complete digital system, combining hardware layer and software layer, are then seen. Also studied: the modeling of a complex system according to different levels of abstraction.

  • Design :
    • Basic architectures, design rules, processing unit, control unit, finite number of states machine.
    • Introduction to a digital system on chip,
    • Method of integrating a specific device,
    • interaction of hardware and software layers,
    • laboratory implementation.
  • Mini-project :
    • Design of a digital circuit: modeling, simulation and logic synthesis.
    • Integration into the complete system: instantiation, software drivers, API (Application Programming Interface).

Learning Outcomes AAv (AAv) ​

  • AAv1 [heures: 15, D1, D2, D3, D4] : The student of the CSP module, at the end of the module, will be able to use the development chain of a programmable system on chip (Intel-FPGA) to design a digital system, from modeling in VHDL language of a specific digital circuit to operation of the complete system on a hardware target when generic files to adapt or files to complete, of known format, are provided

  • AAv2 [heures: 36, D1, D2, D3, D4, E3, F1] : The student of the CSP module, at the end of the module, will be able to propose the synthesizable model of a synchronous digital circuit, in VHDL language , and featuring both combinatorial and sequential functional blocks of a complexity comparable to those seen in the digital circuits course

  • AAv3 [heures: 15, D1, D2, D3, D4, E3, F1] : The student of the CSP module, at the end of the module, will be able to connect a compatible digital circuit to an Avalon interface and will be able to specify the cycle format reading and writing adapted to this digital circuit allowing optimal data exchange

  • AAv4 [heures: 42, C1, C2, D1, D2, D3, D4, E3, F1] : The student of the CSP module, at the end of the module, will be able to design the architecture of a structured, synchronous digital circuit into a processing unit and a control unit, possibly themselves hierarchical, corresponding to specifications provided, with signals and functional blocks clearly identified and specified and minimizing the risk of a metastable state due to the presence possible asynchronous signals or clock domains

  • AAv5 [heures: 15, C2, D1, D2, D3, D4, E3, F1] : The student of the CSP module, at the end of the module, will be able to organize a control unit in a hierarchical and structured form in order to facilitate its development and its test allowing the control of all the elements of the associated processing unit to obtain correct overall operation, processing and control

  • AAv6 [heures: 21, D1, D2, D3, D4, E3, F1] : The student of the CSP module, at the end of the module, will be able to develop in C language a driver (or API: Application Programming Interface) adapted to a given digital circuit in order to be able to use it in a software application written in C language without knowing the details of its hardware implementation

Assessment methods ​

Average of several assessments

Key Words ​

Systems on chip, digital electronics, microprocessor systems, systems architecture, datapath, control unit, finite state machines, VHDL, logic synthesis, pipeline, C.

Prerequisites ​

Basic knowledge of digital electronics: logic gates, flip-flops, Boolean algebra, Karnaugh tables and elementary sequential circuits (counters, shift registers, etc.). Basic knowledge of finite state machines. Knowledge of VHDL and C languages.

Resources ​

Intel-FPGA/Quartus Prime development chain, HDL Modelsim simulation software, QSys system design software, Nios II gen2 processor, NiosII Software Build Tools software development tools, FreeRTOS real-time operating system, development board DE0 CV, FPGA Cyclone V, handouts of courses, tutorials and laboratories.