Synthese Logique

library IEEE;
use IEEE.std_logic_1164.all;

entity icebreaker is
port(  BTN1, BTN2, BTN_N, CLK : in std_logic;
		LED1, LED2, LED3 : out std_logic);
end entity icebreaker;

architecture arch_icebreaker of icebreaker is
signal reset : std_logic;
begin

reset <= not(BTN_N);

process(CLK)
begin
	if reset = '1' then LED1 <= '0'; LED2 <= '0'; LED3 <= '0';
	elsif rising_edge(CLK) then
		if 	  (( BTN1='1' ) and ( BTN2='0' )) then LED1 <= '1'; LED2 <= '0'; LED3 <= '0';
		elsif (( BTN1='1' ) and ( BTN2='1' )) then LED1 <= '0'; LED2 <= '1'; LED3 <= '0';
		elsif (( BTN1='0' ) and ( BTN2='1' )) then LED1 <= '0'; LED2 <= '0'; LED3 <= '1';
		else LED1 <= '0'; LED2 <= '0'; LED3 <= '0';
		end if;
	end if;	
end process;

end arch_icebreaker;

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;



entity icebreaker_tb is
end icebreaker_tb;


architecture arch_icebreaker_tb of icebreaker_tb is

signal BTN1, BTN2, BTN_N, LED1, LED2, LED3, CLK : std_logic;
constant CLK_period : time := 83333 ps; --12MHz

begin

icebreaker_0 : entity icebreaker port map (
BTN1 => BTN1,
BTN2 => BTN2,
BTN_N => BTN_N,
CLK => CLK,
LED1 => LED1,
LED2 => LED2,
LED3 => LED3
);

-- Clock definition.
CLK_process :process
      begin
        CLK <= '0';
        wait for CLK_period / 2;
        CLK <= '1';
        wait for CLK_period / 2;
      end process;

stimuli: process
      begin
      	BTN_N  <= '0'; 
        wait for 1 ms;
		BTN_N  <= '1'; 
        wait for 1 ms;
        BTN1 <= '0'; BTN2 <= '0'; -- Initial conditions.
        wait for 1 ms;
		BTN1 <= '0'; BTN2 <= '1';
        wait for 1 ms;
		BTN1 <= '1'; BTN2 <= '0';
        wait for 1 ms;
        BTN1 <= '1'; BTN2 <= '1';
        wait;
end process;


end arch_icebreaker_tb;